The present invention relates to an information processor having an interruption operating function, and more particularly to an information processor having at least one interface circuit for transmitting an interruption request from an interruption source to the information processor.
An interruption operating function is an important function of an information processor, and is necessary in a microprocessor which is coupled to at least one peripheral equipment. Two types of response systems transmitting a processing request from peripheral equipment have been proposed. One is a system wherein the existence of a processing request from peripheral equipment is monitored on a program at all times by a central processing unit (hereinafter called CPU) in an information processor. This system generally is called a polling system. With this system, the CPU is not capable of working for essential data processing actively, but only monitors the presence of the processing request from the peripheral equipment, and therefore cannot execute programs efficiently at high speed.
The other proposed system is an interruption system. With this system, the CPU does not monitor the peripheral equipment directly, rather, only a processing request is generated from the peripheral equipment in the form of an interruption to the CPU, desired data processing is carried out in the CPU according to an interruption handling program. As compared with the polling system, the interruption system enhances the program execution efficiency.
In this interruption mode, however, the CPU must save the processing status indicating current condition of the CPU in stack means before the interruption processing is started, in order to correctly restart the program execution which is stopped by the interruption. To save the processing status, contents of a program counter, a status word register and other registers which are holding information necessary to execute the program are to be stored in the stack means (for example, a random access memory is generally used) through internal buses in the CPU. Further, the contents stored in the stack means must be returned to the respective registers and the program counter through the internal buses after the interruption operation is terminated.
In the conventional information processor, these saving and returning operations (overhead operations) have been necessarily performed in response to an interruption request. For example, data transmission between peripheral equipment and the CPU is performed in the interruption mode. In this data transmission operation, while the above-described program counter, status word register and other registers are not used, nevertheless the contents of these registers must be stored in the stack means. Therefore, a long overhead time is required in the prior art information processor using the interruption system. Particularly, when a common bus is employed in the CPU as the internal bus, the above-mentioned contents to be stored can not be simultaneously transferred in the stack means, so that a very long period is required for the saving and returning operations.
On the other hand, advances in semiconductor technology have made large scale integrated circuits possible. A microprocessor which has a large number of elements on a single semiconductor chip is provided, and a plurality of peripheral equipment, such as a display unit, a printer unit, a keyboard unit, a motor, may be controlled by a single microprocessor. Such a microprocessor requires an analog to digital or a digital to analog converting function, a timer function, a direct memory access function, a serial data transmission function, or the like. Therefore, a plurality of interface circuits for controlling communications between the CPU and peripheral equipment must be formed on a single semiconductor chip together with the CPU. In this connection, the microprocessor must receive many interruption requests from the peripheral equipments via interface circuits. Therefore, the above-mentioned overhead time becomes longer, and the performance of the microprocessor is further reduced.